`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:49:12 03/31/2014 
// Design Name: 
// Module Name:    lfsr 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LFSR(out,clk,reset,M,seed);

	output reg [3:0] out;

	initial begin
		out [3:0] = 4'b0;
	end

	input clk;
	input reset;
	input [9:0] M;
	input [3:0] seed;

	wire linear_feedback;

	assign linear_feedback = (out[3] ^ out[2]); //NAND gate to randomize

	always @(posedge clk) begin
		if (reset) begin
			out <= seed;
		end
		if (M==450) begin
			out <= {out[2],out[1],
			out[0], linear_feedback};
		end
	end 

endmodule
